1. Field of the Invention
The present invention generally relates to memory architectures in computer systems and, more particularly, to a novel memory storage device and system implementation for enabling a processor device access to multiple memory storage device structures, such as memory caches.
2. Description of the Prior Art
As known, banked memory architectures, e.g., memory cache, comprise a larger memory that is partitioned or divided into distinct blocks that enable more energy efficient use of memory, improves processor cache access time and better exploits parallelism.
It is known that in ASIC memory designs, key design points address the increased overhead in maintaining and implementing a partitioned memory. For example, power and area of the control logic required to implement such banked memory architecture, chip area growth, timing bottlenecks and additional power caused by multiplexed access to memory banks detract from its effectiveness and must be considered in the design.
In present cache system designs, shared banked memory caches aim at distributing accesses either evenly across banks to avoid congestion when using shared randomly accessed data or, provide memory regions assigned to processing elements to avoid congestion by separating accesses. Each of the two architectures provides benefits for a class of applications.
While a banked memory structure assigned and dedicated to each processor is a simple solution, processor access to shared or distributed banked memory architectures is more problematic (in terms of programmability, access time, processing energy, etc.).
In the prior art, U.S. Pat. No. 6,591,345 describes an implementation of a system including a processor device interfaced with a bank-interleaved memory cache, and particularly, a processor enabled to access a bank-interleaved cache containing relatively large strided vectors of data and a method for ensuring maximum access to strided vectors in a bank-interleaved cache memory.
Notwithstanding the innovations of the prior art, it would thus be highly desirable to provide an improved memory access scheme for enabling one or more processor devices to access one or more multiple shared memory banks in a simple and cost-effective manner.
It would further be highly desirable to provide a novel memory architecture that can be configured to provide access distributed across multiple cache memory banks as well as the programmatic capability to assign banks to individual processing elements (e.g., processors).